Title:
WIRING FORMING METHOD
Document Type and Number:
Japanese Patent JP3964226
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a wiring forming method which sufficiently reduces the parasitic capacitance.
SOLUTION: A pattern 2 of photoresist, having connection holes 2a, is formed on a wiring layer 1 on a wafer W. An electroless plating liquid 5 is supplied to the connecting holes 2a of the pattern 2 to bury a metal 6 in the holes 2a. Then the pattern 2 is removed through ashing.
Inventors:
Hiroshi Sato
Application Number:
JP2002048022A
Publication Date:
August 22, 2007
Filing Date:
February 25, 2002
Export Citation:
Assignee:
東京エレクトロン株式会社
International Classes:
H01L23/522; H01L21/768; (IPC1-7): H01L21/768
Domestic Patent References:
| JP5109727A | ||||
| JP63313896A | ||||
| JP7106736A | ||||
| JP5239660A | ||||
| JP4231475A | ||||
| JP2303181A |
Attorney, Agent or Firm:
Saichi Suyama