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Patent Searching and Data


Title:
WIRING LAYOUT IN PRINTED WIRING BOARD
Document Type and Number:
Japanese Patent JPH04243483
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of pins to be connected that cannot be connected and to reduce an influence of the interference of wiring patterns on computer operation.

CONSTITUTION: A processing box 1-1 determines the minimum rectangular area that includes outer contours of parts to be laid out. A processing box 1-2 determines an area on a printed wiring board for fabricating parts. A processing box 1-3 determines a vacant area in the printed wiring board from a total of summing up the minimum rectangular area for every part and an area in the board available for fabricating parts. A processing box 1-4 figures out areas that are reserved in advance around parts for wiring. A processing box 1-5 lays out reserved wiring areas for parts so as not to overlap one another. A processing box 1-7, when there remain unlaid parts, contracts wiring areas reserved around parts to relay out reserved wiring areas.


Inventors:
TERAI TAKEE
Application Number:
JP415291A
Publication Date:
August 31, 1992
Filing Date:
January 18, 1991
Export Citation:
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Assignee:
NEC SOFTWARE HOKURIKU
International Classes:
G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Shin Uchihara