Title:
WIRING LAYOUT METHOD AND DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3223888
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit wiring layout method and a device, where functional blocks can be easily relocated so as to enhance a semiconductor integrated circuit in wiring capacitance without deteriorating the semiconductor integrated circuit in wiring density.
SOLUTION: Pre-functional blocks are previously stored in the library of a wiring layout device. A pre-functional block 22b has the same functions with a pre-functional block 22a, and the pre-functional block 22a is so designed as to be larger in drive capacity but smaller in wiring capacity than the pre- functional block 22b. The pre-functional block 22b smaller in drive capacity than the pre-functional block 22a is formed taking the type, direction, shape, and size of a base into consideration so as to be arranged without fail at a site where the pre-functional block 22b is arranged.
Inventors:
Mikiko Tanaka
Application Number:
JP26951398A
Publication Date:
October 29, 2001
Filing Date:
September 24, 1998
Export Citation:
Assignee:
NEC
International Classes:
H01L21/82; G06F17/50; (IPC1-7): H01L21/82; G06F17/50
Domestic Patent References:
| JP9251478A | ||||
| JP685216A | ||||
| JP613584A | ||||
| JP4320060A | ||||
| JP794586A |
Attorney, Agent or Firm:
Masanori Fujimaki