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Patent Searching and Data


Title:
WIRING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH06204338
Kind Code:
A
Abstract:

PURPOSE: To provide an automatic wiring processing method which enables a large scale semiconductor integrated circuit to be automatically wired in shorter processing time and a computer to be minimized in memory.

CONSTITUTION: A semiconductor integrated circuit wiring processing method is composed of a rough wiring method which roughly determines the path of wiring and a detailed wiring method which determines the actual position of a wiring layout on the basis of the determined result of the rough wiring method, wherein the rough wiring method is composed of an overall rough wiring 103 which covers all the wiring region of a semiconductor integrated circuit chip and a partial region rough wiring 106 which covers a partial region of the semiconductor integrated circuit chip on the basis of the result obtained by the overall rough wiring 103.


Inventors:
SHINJO KEISUKE
Application Number:
JP92993A
Publication Date:
July 22, 1994
Filing Date:
January 07, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/82; G06F17/50; (IPC1-7): H01L21/82; G06F15/60
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)