Title:
WIRING MUTUAL CONNECTION STRUCTURE
Document Type and Number:
Japanese Patent JPS60263491
Kind Code:
A
Abstract:
A method for establishing interconnections in the vicinity of congested clusters of pins in a printed circuit (10) using an extended escape region E' in combination with an escape region E containing the pins and a global region surrounding the printed circuit 10. The extended escape region includes wire path segments in one signal plane of a plane pair which may enter the extended escape region from the escape region in a direction parallel or perpendicular to the predominant direction of wiring in that plane. All wire segments exit the extended escape region to said global region in the predominant direction for the signal plane on which the interconnection is disposed.
Inventors:
RARUFU RINSUKAA
ROJIYAA SHIYAAMAN RATSUTAA
ROJIYAA SHIYAAMAN RATSUTAA
Application Number:
JP7455885A
Publication Date:
December 26, 1985
Filing Date:
April 10, 1985
Export Citation:
Assignee:
IBM
International Classes:
G06F17/50; H01L21/3205; H05K3/00; H01L21/82; H01L23/52; H05K1/02; H05K3/46; (IPC1-7): H01L21/88; H05K1/02
Domestic Patent References:
| JPS5522174U | 1980-02-13 | |||
| JPS5918880A | 1984-01-31 | |||
| JPS5717157A | 1982-01-28 |
Attorney, Agent or Firm:
Kiyoshi Goda (4 outside)