Title:
AUTOMATIC POSITIONING AND WIRING
Document Type and Number:
Japanese Patent JP3130841
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an counter-EM, automatic positioning and wiring method which can avoid reduction of a wiring performance caused by an excessive EM measure in a functional block.
SOLUTION: After a deciding step S2 are provided a capacity extracting step S3 of finding actual wiring lengths between functional blocks from an automatic positioning and wiring result 3 and outputting as an output load capacity a sum of a wiring capacity and an input terminal capacity of a next stage, and a pattern changing step S4 for determining a pattern which satisfies EM standards for each of the functional blocks from an output load capacity 4, a table 5 showing the output load capacity 4 and an EM measure pattern parameter associated with the capacity 4 and an operating frequency 6 and changing before-EM measure pattern for each functional block to an after-EM measure pattern.
Inventors:
Hiroshi Ito
Application Number:
JP26559097A
Publication Date:
January 31, 2001
Filing Date:
September 30, 1997
Export Citation:
Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
H01L21/82; G06F17/50; (IPC1-7): H01L21/82
Domestic Patent References:
| JP4107953A | ||||
| JP6259499A | ||||
| JP6349947A | ||||
| JP8264656A | ||||
| JP5211236A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)