Title:
クロスバー・アレイ抵抗スイッチング・デバイスに対するラップアラウンド上部電極ライン
Document Type and Number:
Japanese Patent JP7194485
Kind Code:
B2
Abstract:
A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.
Inventors:
Takashi Ando
Yang, Qichao
Briggs, Benjamin
Rizzolo, Michael
Lawrence, Clevenger
Yang, Qichao
Briggs, Benjamin
Rizzolo, Michael
Lawrence, Clevenger
Application Number:
JP2020524382A
Publication Date:
December 22, 2022
Filing Date:
November 01, 2018
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
H01L21/8239; H01L21/3205; H01L21/768; H01L23/532; H01L27/105; H01L45/00; H01L49/00
Domestic Patent References:
| JP2017510983A |
Foreign References:
| WO2012073503A1 | ||||
| US20130112935 | ||||
| US20150243708 | ||||
| WO2015130455A1 | ||||
| EP3742507A1 | ||||
| WO2015067051A1 |
Attorney, Agent or Firm:
Tadashi Taneichi