Title:
WRITING FOR MERGED TYPE NON-VOLATILE MEMORY MATRIX
Document Type and Number:
Japanese Patent JPS6199997
Kind Code:
A
Abstract:
Writing of a selected cell for example (C1) takes place by applying a high positive drain voltage to the entire row (FD 1) of cells having a common drain (D) including said selected cell and a zero gate voltage to the entire row (FG1) of cells having a common gate (G) including said selected cell. The other rows 61 (FD2) of cells having common drains have zero drain voltage. To prevent writing of the selected cell causing changes in the unselected cells of the other rows (FG2) of cells with common gates the latter (C2-C4) are subjected to a gate voltage intermediate between said positive voltage and said zero voltage. Said intermediate voltage slows the passage of charges from and to the floating gate (F) of said cells (C2-C4), preventing change of state.
Inventors:
ANDOREA RABAGURIA
Application Number:
JP23465985A
Publication Date:
May 19, 1986
Filing Date:
October 22, 1985
Export Citation:
Assignee:
S JI S MIKUROERETSUTORONIKA SP
International Classes:
G11C16/02; G11C16/04; G11C17/00; H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): G11C17/00; H01L29/78
Attorney, Agent or Firm:
Shinichi Ogawa
Previous Patent: The valve and filter system for a gravity sending spray container
Next Patent: POLYESTER AND POLYURETHANE RESIN
Next Patent: POLYESTER AND POLYURETHANE RESIN