PURPOSE: To realize the high-speed processing of data, by writing the subsequent blocks at one time into a buffer memory.

CONSTITUTION: Circuits 1W9 form a buffer memory. In case the data requested from a CPU1 for reading does not exist in a buffer memory, an address of 20 bits (Nos. 0W19) of a subsequent block address register NAR17 is sent to a main storage device 12. Then the data of the block to which the above-mentioned address belongs is read, and a replacement control register 4 is inspected to detect the oldest block. The data of the subsequent blocks given from the device 12 are written into the block corresponding to a data array 7. The value of 12 bits (Nos. 0W11) of the NAR17 is written into an address array 2, and at the same time the maintenance is performed for the register 4.