Title:
ＳＳＤ通信プロトコルのためのＸＯＲ基盤のスクランブリング及びディスクランブリング方法及びシステム
Document Type and Number:
Japanese Patent JP6633967
Kind Code:
B2
Abstract:
Example embodiments for descrambling and scrambling a memory channel include executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data. The training mode inputs all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device. The scrambled training data are equal to the XOR vectors corresponding to those memory locations. The scrambled training data is received over the memory channel by the memory device and stored as the XOR vectors for each corresponding memory location. During a functional mode, the scrambled data is received over the memory channel for a specified memory location and the XOR vector stored for the specified memory location is used to descramble the scrambled data prior to writing to the specified memory location.
Inventors:
Zhi Zhi
Beckerman, Michael
Swerbrick, Ian
Hanson, Craig
Beckerman, Michael
Swerbrick, Ian
Hanson, Craig
Application Number:
JP2016093038A
Publication Date:
January 22, 2020
Filing Date:
May 06, 2016
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H04L9/20; G06F3/08; G06F13/10; G06F21/60; G06F21/78
Domestic Patent References:
| JP2008010923A | ||||
| JP2002091828A | ||||
| JP2010512584A | ||||
| JP2005130059A | ||||
| JP2005504373A |
Attorney, Agent or Firm:
Kyosei International Patent Office