Title:
ZERO FLAG GENERATING ADDER/SUBTRACTOR
Document Type and Number:
Japanese Patent JP3298119
Kind Code:
B2
Abstract:
PURPOSE: To generate a zero flag at high speed by adding a small number of circuits.
CONSTITUTION: This adder/subtractor is an adder/subtractor to operate addition or subtraction to inputted two pieces of data, and to detect the zero flag representing the fact that a result shows zero, and it is a zero flag generating adder/subtractor equipped with a means 101 which finds first overflow from the most significant digit by computation to find, a means 102 which finds second overflow from the most significant digit by the computation to find a result less by one than the one in the computation to find, and a means 103 which detects the zero flag from the first and second overflow. Thereby, it is possible to generate the zero flag at high speed only by adding a small number of circuits.
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Inventors:
Takashi Taniguchi
Application Number:
JP28258591A
Publication Date:
July 02, 2002
Filing Date:
October 29, 1991
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F7/00; G06F7/38; G06F7/50; G06F7/508; (IPC1-7): G06F7/50; G06F7/38
Domestic Patent References:
| JP3142626A |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)