Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2513420
Kind Code:
B2
Abstract:
PURPOSE: To design optimum impurity concentration in each of a well and element isolation and 'reduction of the distance between PN isolations' which isolates an N-type transistor from a P-type transistor and reduce the number of a photolithography steps and shorten the manufacturing process.
CONSTITUTION: Impurity concentration of a well and impurity concentration in an element isolation region are designed independently, respectively, to form the well and element isolation region in a self-alignment manner, and the distance between an element isolating oxide film 13 end and a P well 6 end and an N well end is set without allowing for misregistration of mask in a photolithography step, and the number of photolithography steps is decreased to form a CMOS transistor.
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Inventors:
HAMATAKE NOBUHISA
Application Number:
JP19561993A
Publication Date:
July 03, 1996
Filing Date:
July 14, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/8238; H01L21/265; H01L21/266; H01L21/76; H01L27/092; (IPC1-7): H01L21/8238; H01L21/266; H01L21/76; H01L27/092
Attorney, Agent or Firm:
Noriaki Miyakoshi