Title:
PLL回路及びこれに用いられる自動バイアス調整回路
Document Type and Number:
Japanese Patent JP4270339
Kind Code:
B2
Abstract:
A bias current IB additionally provided to a current-controlled circuit 13 in a PLL circuit is the sum of bias currents IB1 and IB2 which are generated by a bias adjustment circuit (18, 19, 20, 21 and 22) and a bias current generating circuit (23 and 24), respectively. The bias adjustment circuit adjusts the bias current IB1 in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit 23 generating a bias voltage VT and a circuit 24 converting the VT into a current IB2, wherein the temperature characteristic of the bias voltage VT is opposite to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.
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Inventors:
Hiroto Azuma
Hideki Ishida
Hideki Ishida
Application Number:
JP2000398301A
Publication Date:
May 27, 2009
Filing Date:
December 27, 2000
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03L7/099; H03L1/02; H03L7/10; H03L7/189; H03L7/089
Domestic Patent References:
| JP10084278A | ||||
| JP2000216675A | ||||
| JP2000201072A | ||||
| JP11017538A | ||||
| JP11127076A | ||||
| JP2000252819A | ||||
| JP11177416A |
Attorney, Agent or Firm:
Shinkichi Matsumoto