Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3174293
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce contact resistance and prevent generation of deterioration with time in the contact resistance.
SOLUTION: A buffer layer 12 consisting of undoped In0.52Al0.48As of 500 nm in thickness, a channel layer 13 consisting of undoped In0.53Ga0.47As of 30 nm in thickness, an N-type delta doped layer 15 which is used for obtaining a specified carrier concentration while the distance from a gate electrode is shortened, a Schottky layer 16 consisting of undoped In0.52Al0.48As, and a cap layer 17 consisting of Si doped N-type In0.53Ga0.47As of 50 nm in thickness, are laminated sequentially on a main surface of a semi-insulating substrate 11 consisting of Fe doped InP. A protective layer 18 consisting of Si doped N-type GaAs of 7.5 nm in thickness and protects a cap layer 17 is arranged between the cap layer 17 and a source electrode 22 and between the cap layer 17 and a drain electrode 23.
Inventors:
Mitsuru Tanabe
Application Number:
JP525398A
Publication Date:
June 11, 2001
Filing Date:
January 14, 1998
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L29/43; H01L21/28; H01L21/338; H01L29/778; H01L29/812; (IPC1-7): H01L29/778; H01L21/338; H01L29/43
Domestic Patent References:
| JP8274025A | ||||
| JP7263663A | ||||
| JP818034A |
Other References:
【文献】米国特許5789767(US,A)
【文献】米国特許5856681(US,A)
【文献】米国特許5856681(US,A)
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)