Title:
A circuit emulation device, the circuit emulation method, and a circuit emulation program
Document Type and Number:
Japanese Patent JP5935319
Kind Code:
B2
Abstract:
A circuit emulation apparatus includes an emulator unit configured to emulate an operation of a circuit, a replacement unit configured to replace one or more redundant bits with a predetermined bit pattern when information bits and the one or more redundant bits of read data that is read from a first memory by the circuit are all zeros, and a supply unit configured to supply the information bits and the predetermined bit pattern as the read data to the circuit.
More Like This:
| JPH0373046 | LOGIC SIMULATION METHOD FOR MEMORY CELL |
| JP3693005 | WIRE HARNESS DESIGNING METHOD |
Inventors:
Katsuya Suga
Application Number:
JP2011284409A
Publication Date:
June 15, 2016
Filing Date:
December 26, 2011
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50; H03M13/09
Domestic Patent References:
| JP62062499A | ||||
| JP61259352A | ||||
| JP2009064238A |
Foreign References:
| US7991605 |
Attorney, Agent or Firm:
Tadahiko Ito
Akinori Yamaguchi
Akinori Yamaguchi
Previous Patent: The electrolysis solution for rechargeable lithium-ion batteries, a rechargeable lithium-ion battery...
Next Patent: JPS5935320
Next Patent: JPS5935320