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Title:
クロック制御方法と分周回路及びPLL回路
Document Type and Number:
Japanese Patent JP4587620
Kind Code:
B2
Abstract:
A PLL circuit includes phase comparator (103) having a first input terminal to which a reference clock is applied; charge pump (104) generating a voltage conforming to a phase difference output from the phase comparator; loop filter (105); VCO (106); frequency dividing circuit (107), to which an output clock of the VCO is input, performing frequency-division by P; A counter (109) dividing the output of the frequency dividing circuit by a second value A; circuits (121,122) generating two signals, which have a phase difference equivalent to one period of the P-frequency-divided output of the frequency dividing circuit, whenever frequency-division by A is performed by the A counter; and interpolator (123), to which the two generated signals are input, producing an output signal of a phase obtained by interpolating the phase difference between the two signals in accordance with an interior division ratio set by a control signal.

Inventors:
Takahiro Saeki
Application Number:
JP2001273771A
Publication Date:
November 24, 2010
Filing Date:
September 10, 2001
Export Citation:
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Assignee:
Renesas Electronics Corporation
International Classes:
G06F1/08; H03K23/64; G06F7/68; H03K5/00; H03L7/08; H03L7/081; H03L7/183; H03L7/197; H03L7/089
Domestic Patent References:
JP669788A
JP6120815A
JP3261222A
JP10247850A
JP1198007A
JP62112423A
Other References:
S.Sidiropoulos他,「A Semidigital Dual Delay-Locked Loop」,IEEE Journal of Solid-State Circuits,米国,IEEE,1997年11月,Vol.32、No.11,P1683-1692,レプリカバイアス型インターポレータ
K.Yamaguchi他,「2.5GHz 4-phase Clock Generator with Scalable and No Feedback Loop Architecture」,2001 IEEE International Solid-State Circuit Conference,米国,IEEE,2001年 2月 7日,Session25,レプリカバイアス型インターポレータ
Attorney, Agent or Firm:
Kato Asamichi