Title:
クロック信号分周回路及びクロック信号分周方法
Document Type and Number:
Japanese Patent JP5494858
Kind Code:
B2
Abstract:
To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and M are integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.
Inventors:
Mitsufumi Shibayama
Koichi Nose
Koichi Nose
Application Number:
JP2013064291A
Publication Date:
May 21, 2014
Filing Date:
March 26, 2013
Export Citation:
Assignee:
NEC
International Classes:
H03K21/00; G06F1/08; H03K23/64
Domestic Patent References:
| JP9223959A | ||||
| JP3003517A | ||||
| JP5240850B2 |
Attorney, Agent or Firm:
Isamu Takahashi