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Title:
ディレイロックドループ、当該ディレイロックドループを含む半導体装置およびクロック同期により動作するシステムのための制御方法
Document Type and Number:
Japanese Patent JP4592179
Kind Code:
B2
Abstract:
A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time (discontinuous skipping thereof) if a metastable state should occur.

Inventors:
Yasuhiko Tsukikawa
Application Number:
JP2000385020A
Publication Date:
December 01, 2010
Filing Date:
December 19, 2000
Export Citation:
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Assignee:
Renesas Electronics Corporation
International Classes:
G11C11/407; H03L7/081; G06F1/10; G11C7/22; G11C8/00; G11C11/4076; H03K5/00; H03K5/14; H03K23/64; H03M7/16
Domestic Patent References:
JP7506476A
JP11007768A
JP9238053A
JP11355131A
JP8097715A
JP2000122750A
JP11122750A
JP2000163961A
JP11355133A
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Masayuki Sakai
Nobuo Arakawa
Masato Sasaki
Hisato Noda