Title:
計数装置及びその駆動方法
Document Type and Number:
Japanese Patent JP4240657
Kind Code:
B2
Abstract:
A hold/reset mode selection counter includes a counter unit composed of a plurality of counter blocks to perform a counting operation, a mode selection unit that detects a count enable signal length, and a control unit that enables or disables the counter unit. A detection unit generates a signal that holds or pauses the counter unit. The hold/reset mode selection counter controls the counting operation and a reset operation so that the operations are performed only when necessary, and a number of the counter blocks can be reduced. Thus, the hold/reset mode selection counter does not unconditionally perform a counting operation in accordance with an enable signal or perform a circular counting operation.
Inventors:
Yong-Hwan Choi
Application Number:
JP14474499A
Publication Date:
March 18, 2009
Filing Date:
May 25, 1999
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
H03K21/38; H03K23/00; H03K23/40
Domestic Patent References:
| JP583124A | ||||
| JP313122A | ||||
| JP61251230A | ||||
| JP6253519A |
Attorney, Agent or Firm:
Tomijio Sasashima
Haruyuki Nishiyama
Moriaki Ogawa
Hiroji Nakagawa
Haruyuki Nishiyama
Moriaki Ogawa
Hiroji Nakagawa