Title:
オクターブ境界を越えて拡張された同期範囲を有する分周器
Document Type and Number:
Japanese Patent JP2014510439
Kind Code:
A
Abstract:
A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and additional circuit elements to correctly divide an input frequency by a divisor on successive output cycles while the divisor transitions across an octave boundary. The frequency divider creates a divide-by-1 mode for unused divide-by-1/2/3 cells in the series of cells. The divide-by-1 mode passes the input clock in the unused latches of each unused divide-by-1/2/3 cell as opposed to having each unused divide-by-1/2/3 cell implement divide-by-3 mode.
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| JPS58117732 | FREQUENCY DIVIDER |
| JPS61263320 | SEMICONDUCTOR INTEGRATED CIRCUIT FOR FREQUENCY DIVISION |
Inventors:
Cabin, Mark Es
Application Number:
JP2013551286A
Publication Date:
April 24, 2014
Filing Date:
January 24, 2012
Export Citation:
Assignee:
Coherent Logics Incorporated
International Classes:
H03K23/64; G06F1/08
Domestic Patent References:
| JP2002509376A | 2002-03-26 | |||
| JP2003526239A | 2003-09-02 | |||
| JP2002509376A | 2002-03-26 | |||
| JP2003526239A | 2003-09-02 |
Foreign References:
| US20050258878A1 | 2005-11-24 | |||
| US20070008040A1 | 2007-01-11 | |||
| US5948046A | 1999-09-07 | |||
| US20050258878A1 | 2005-11-24 | |||
| US20070008040A1 | 2007-01-11 | |||
| US5948046A | 1999-09-07 |
Other References:
JPN5014003566; ＹＡＮＧ ＹＵ-ＣＨＥ: 'Ａ ＱＵＡＮＴＩＺＡＴＩＯＮ ＮＯＩＳＥ ＳＵＰＰＲＥＳＳＩＯＮ ＴＥＣＨＮＩＱＵＥ ＦＯＲ ＦＲＡＣＴＩＯＮＡＬ-ＦＲＥＱＵＥＮＣＹ ＳＹＮＴＨＥＳＩＺＥＲＳ' ＩＥＥＥ ＪＯＵＲＮＡＬ ＯＦ ＳＯＬＩＤ-ＳＴＡＴＥ ＣＩＲＣＵＩＴＳ Ｖ４１ Ｎ１１, 20061101, Ｐ２５００-２５１１, ＩＥＥＥ ＳＥＲＶＩＣＥ ＣＥＮＴＥＲ
JPN5014003567; ＡＭＲ Ｎ ＦＡＨＩＭ: 'Ａ ＷＩＤＥＢＡＮＤ ＳＩＧＭＡ-ＤＥＬＴＡ ＰＨＡＳＥ-ＬＯＣＫＥＤ-ＬＯＯＰ ＭＯＤＵＬＡＴＯＲ ＦＯＲ ＷＩＲＥＬＥＳＳ ＡＰＰＬＩＣＡＴＩＯＮＳ' ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮＳ ＯＮ ＣＩＲＣＵＩＴＳ ＡＮＤ ＳＹＳＴＥＭＳ ＩＩ； ＡＮＡＬＯＧ ＡＮＤ ＤＩＧＩＴＡＬ ＳＩＧＮＡＬ ＰＲＯＣＥＳＳＩＮＧ Ｖ５０ Ｎ２, 20030201, ＩＮＳＴＩＴＵＴＥ ＯＦ ＥＬＥＣＴＲＩＣＡＬ ＡＮＤ ＥＬＥＣＴＲＯＮＩＣＳ ＥＮＧＩＮＥＥＲＳ
JPN5014003568; ＭＯＨＡＭＥＤ ＥＩＳＳＡ: 'Ａ ＴＥＣＨＮＩＱＵＥ ＦＯＲ ＲＯＢＵＳＴ ＤＩＶＩＳＩＯＮ ＲＡＴＩＯ ＳＷＩＴＣＨＩＮＧ ＩＮ ＭＵＬＴＩ ＭＯＤＵＬＵＳ ＤＩＶＩＤＥＲＳ ＷＩＴＨ ＭＯＤＵＬＵＳ ＥＸＴＥＮＳＩＯＮ' ２０１０ ＩＮＴＥＲＮＡＴＩＯＮＡＬ ＣＯＮＦＥＲＥＮＣＥ ＯＮ ＭＩＣＲＯＥＬＥＣＴＲＯＮＩＣＳ （ＩＣＭ） , 20101219, Ｐ８４-８７, ＩＥＥＥ
JPN5014003566; ＹＡＮＧ ＹＵ-ＣＨＥ: 'Ａ ＱＵＡＮＴＩＺＡＴＩＯＮ ＮＯＩＳＥ ＳＵＰＰＲＥＳＳＩＯＮ ＴＥＣＨＮＩＱＵＥ ＦＯＲ ＦＲＡＣＴＩＯＮＡＬ-ＦＲＥＱＵＥＮＣＹ ＳＹＮＴＨＥＳＩＺＥＲＳ' ＩＥＥＥ ＪＯＵＲＮＡＬ ＯＦ ＳＯＬＩＤ-ＳＴＡＴＥ ＣＩＲＣＵＩＴＳ Ｖ４１ Ｎ１１, 20061101, Ｐ２５００-２５１１, ＩＥＥＥ ＳＥＲＶＩＣＥ ＣＥＮＴＥＲ
JPN5014003567; ＡＭＲ Ｎ ＦＡＨＩＭ: 'Ａ ＷＩＤＥＢＡＮＤ ＳＩＧＭＡ-ＤＥＬＴＡ ＰＨＡＳＥ-ＬＯＣＫＥＤ-ＬＯＯＰ ＭＯＤＵＬＡＴＯＲ ＦＯＲ ＷＩＲＥＬＥＳＳ ＡＰＰＬＩＣＡＴＩＯＮＳ' ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮＳ ＯＮ ＣＩＲＣＵＩＴＳ ＡＮＤ ＳＹＳＴＥＭＳ ＩＩ； ＡＮＡＬＯＧ ＡＮＤ ＤＩＧＩＴＡＬ ＳＩＧＮＡＬ ＰＲＯＣＥＳＳＩＮＧ Ｖ５０ Ｎ２, 20030201, ＩＮＳＴＩＴＵＴＥ ＯＦ ＥＬＥＣＴＲＩＣＡＬ ＡＮＤ ＥＬＥＣＴＲＯＮＩＣＳ ＥＮＧＩＮＥＥＲＳ
JPN5014003568; ＭＯＨＡＭＥＤ ＥＩＳＳＡ: 'Ａ ＴＥＣＨＮＩＱＵＥ ＦＯＲ ＲＯＢＵＳＴ ＤＩＶＩＳＩＯＮ ＲＡＴＩＯ ＳＷＩＴＣＨＩＮＧ ＩＮ ＭＵＬＴＩ ＭＯＤＵＬＵＳ ＤＩＶＩＤＥＲＳ ＷＩＴＨ ＭＯＤＵＬＵＳ ＥＸＴＥＮＳＩＯＮ' ２０１０ ＩＮＴＥＲＮＡＴＩＯＮＡＬ ＣＯＮＦＥＲＥＮＣＥ ＯＮ ＭＩＣＲＯＥＬＥＣＴＲＯＮＩＣＳ （ＩＣＭ） , 20101219, Ｐ８４-８７, ＩＥＥＥ
JPN5014003567; ＡＭＲ Ｎ ＦＡＨＩＭ: 'Ａ ＷＩＤＥＢＡＮＤ ＳＩＧＭＡ-ＤＥＬＴＡ ＰＨＡＳＥ-ＬＯＣＫＥＤ-ＬＯＯＰ ＭＯＤＵＬＡＴＯＲ ＦＯＲ ＷＩＲＥＬＥＳＳ ＡＰＰＬＩＣＡＴＩＯＮＳ' ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮＳ ＯＮ ＣＩＲＣＵＩＴＳ ＡＮＤ ＳＹＳＴＥＭＳ ＩＩ； ＡＮＡＬＯＧ ＡＮＤ ＤＩＧＩＴＡＬ ＳＩＧＮＡＬ ＰＲＯＣＥＳＳＩＮＧ Ｖ５０ Ｎ２, 20030201, ＩＮＳＴＩＴＵＴＥ ＯＦ ＥＬＥＣＴＲＩＣＡＬ ＡＮＤ ＥＬＥＣＴＲＯＮＩＣＳ ＥＮＧＩＮＥＥＲＳ
JPN5014003568; ＭＯＨＡＭＥＤ ＥＩＳＳＡ: 'Ａ ＴＥＣＨＮＩＱＵＥ ＦＯＲ ＲＯＢＵＳＴ ＤＩＶＩＳＩＯＮ ＲＡＴＩＯ ＳＷＩＴＣＨＩＮＧ ＩＮ ＭＵＬＴＩ ＭＯＤＵＬＵＳ ＤＩＶＩＤＥＲＳ ＷＩＴＨ ＭＯＤＵＬＵＳ ＥＸＴＥＮＳＩＯＮ' ２０１０ ＩＮＴＥＲＮＡＴＩＯＮＡＬ ＣＯＮＦＥＲＥＮＣＥ ＯＮ ＭＩＣＲＯＥＬＥＣＴＲＯＮＩＣＳ （ＩＣＭ） , 20101219, Ｐ８４-８７, ＩＥＥＥ
JPN5014003566; ＹＡＮＧ ＹＵ-ＣＨＥ: 'Ａ ＱＵＡＮＴＩＺＡＴＩＯＮ ＮＯＩＳＥ ＳＵＰＰＲＥＳＳＩＯＮ ＴＥＣＨＮＩＱＵＥ ＦＯＲ ＦＲＡＣＴＩＯＮＡＬ-ＦＲＥＱＵＥＮＣＹ ＳＹＮＴＨＥＳＩＺＥＲＳ' ＩＥＥＥ ＪＯＵＲＮＡＬ ＯＦ ＳＯＬＩＤ-ＳＴＡＴＥ ＣＩＲＣＵＩＴＳ Ｖ４１ Ｎ１１, 20061101, Ｐ２５００-２５１１, ＩＥＥＥ ＳＥＲＶＩＣＥ ＣＥＮＴＥＲ
JPN5014003567; ＡＭＲ Ｎ ＦＡＨＩＭ: 'Ａ ＷＩＤＥＢＡＮＤ ＳＩＧＭＡ-ＤＥＬＴＡ ＰＨＡＳＥ-ＬＯＣＫＥＤ-ＬＯＯＰ ＭＯＤＵＬＡＴＯＲ ＦＯＲ ＷＩＲＥＬＥＳＳ ＡＰＰＬＩＣＡＴＩＯＮＳ' ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮＳ ＯＮ ＣＩＲＣＵＩＴＳ ＡＮＤ ＳＹＳＴＥＭＳ ＩＩ； ＡＮＡＬＯＧ ＡＮＤ ＤＩＧＩＴＡＬ ＳＩＧＮＡＬ ＰＲＯＣＥＳＳＩＮＧ Ｖ５０ Ｎ２, 20030201, ＩＮＳＴＩＴＵＴＥ ＯＦ ＥＬＥＣＴＲＩＣＡＬ ＡＮＤ ＥＬＥＣＴＲＯＮＩＣＳ ＥＮＧＩＮＥＥＲＳ
JPN5014003568; ＭＯＨＡＭＥＤ ＥＩＳＳＡ: 'Ａ ＴＥＣＨＮＩＱＵＥ ＦＯＲ ＲＯＢＵＳＴ ＤＩＶＩＳＩＯＮ ＲＡＴＩＯ ＳＷＩＴＣＨＩＮＧ ＩＮ ＭＵＬＴＩ ＭＯＤＵＬＵＳ ＤＩＶＩＤＥＲＳ ＷＩＴＨ ＭＯＤＵＬＵＳ ＥＸＴＥＮＳＩＯＮ' ２０１０ ＩＮＴＥＲＮＡＴＩＯＮＡＬ ＣＯＮＦＥＲＥＮＣＥ ＯＮ ＭＩＣＲＯＥＬＥＣＴＲＯＮＩＣＳ （ＩＣＭ） , 20101219, Ｐ８４-８７, ＩＥＥＥ
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Shigeki Yamakawa