Title:
A data processing device, a micro controller, and a semiconductor device
Document Type and Number:
Japanese Patent JP6072661
Kind Code:
B2
Abstract:
In order to perform easily power cutoff of a device configuring a data processing system and to improve the power reduction effect at standby, the data processing system is configured with a microcontroller, a memory IC including a nonvolatile RAM array, and a power supply unit capable of controlling the power supply to the microcontroller and the memory IC, separately. When a control signal to control read and write of data to the nonvolatile RAM array is at a high level, the memory IC is enabled read and write of data to the nonvolatile RAM array. When the control signal is at a low level, the memory IC is disenabled read and write of data to the nonvolatile RAM array. The microcontroller sets the control signal at a low level, when the memory IC is shifted to a standby state by the power supply unit.
Inventors:
Haraguchi University
Hayashi Isamu
Hiroyuki Kawai
Hayashi Isamu
Hiroyuki Kawai
Application Number:
JP2013204650A
Publication Date:
February 01, 2017
Filing Date:
September 30, 2013
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G06F12/00
Domestic Patent References:
| JP2012195050A | ||||
| JP2012505472A | ||||
| JP201330087A | ||||
| JP200883998A |
Foreign References:
| US6073243 | ||||
| US20010025333 |
Attorney, Agent or Firm:
Shizuyo Tamamura
Previous Patent: A hardening resin constituent and the constituent for hard courts
Next Patent: AUTOMATIC POURING DEVICE
Next Patent: AUTOMATIC POURING DEVICE