Title:
A data processing system which has the error detection of setting information on peripheral equipment
Document Type and Number:
Japanese Patent JP6021241
Kind Code:
B2
Abstract:
In a data processing system (101) including a first master (103) operably coupled to a peripheral bus interface and a plurality of peripherals (125, 137, 129, 133) operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface (113), a method includes initiating a write, by the first master, of configuration information to a first peripheral of the plurality of peripherals. In response to initiating the write, the configuration information is provided via the peripheral bus interface for storage into the first peripheral, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface. The provided configuration information is stored in the first peripheral, and the first error syndrome is stored in storage circuitry of the peripheral bus interface. The first error syndrome can be used to check the integrity of configuration information during subsequent error checking.
Inventors:
Gary Elle Miller
Application Number:
JP2011165717A
Publication Date:
November 09, 2016
Filing Date:
July 28, 2011
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G06F11/00; G06F13/00
Domestic Patent References:
| JP2008052389A | ||||
| JP62163115A |
Foreign References:
| US7426678 |
Attorney, Agent or Firm:
Atsushi Honda