Title:
差分マンチェスタエンコードされた信号をダウンサンプリングするためのデコーダ回路
Document Type and Number:
Japanese Patent JP5859124
Kind Code:
B2
Abstract:
Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.
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Inventors:
Gobindan Magali, Salvendra
Soma, Beelender Kumar
Arigabe, Heramba
Grant, Douglas M
Soma, Beelender Kumar
Arigabe, Heramba
Grant, Douglas M
Application Number:
JP2014522814A
Publication Date:
February 10, 2016
Filing Date:
February 14, 2012
Export Citation:
Assignee:
XILINX INCORPORATED
International Classes:
H03M5/12; H04L25/49
Domestic Patent References:
| JP11088446A | ||||
| JP2006086844A | ||||
| JP2004328174A | ||||
| JP2002261845A |
Foreign References:
| US6933866 | ||||
| US20080137724 |
Attorney, Agent or Firm:
Fukami patent office