Title:
フェーズロックループ回路の遅延故障検出装置及び方法
Document Type and Number:
Japanese Patent JP4513077
Kind Code:
B2
Abstract:
There is provided a method and an apparatus for detecting a delay fault in a phase-locked loop circuit. A frequency impulse is applied to the PLL circuit under test as a reference clock, and a waveform of a signal outputted from the PLL circuit under test is transformed to an analytic signal to estimate its instantaneous phase. A linear phase is estimated from the estimated instantaneous phase, and the estimated linear phase is removed from the estimated instantaneous phase to obtain a fluctuation term of the instantaneous phase. A delay fault is detected by comparing a time duration during which the PLL circuit stays in a state of oscillating a certain frequency with the time duration during which a fault-free PLL circuit stays in a state of oscillating a certain frequency.
Inventors:
Takahiro Yamaguchi
Mani Soma
Masahiro Ishida
Mani Soma
Masahiro Ishida
Application Number:
JP2000038415A
Publication Date:
July 28, 2010
Filing Date:
February 16, 2000
Export Citation:
Assignee:
Advantest Corporation
Mani Soma
Mani Soma
International Classes:
G01R31/316; G01R31/28; G01R31/30; H03L7/08; G01R25/00
Domestic Patent References:
| JP2032078U |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation
Minoru Inagaki
Minoru Inagaki
Minoru Inagaki
Minoru Inagaki