Title:
ΔΣ TYPE AD CONVERTER
Document Type and Number:
Japanese Patent JP2017225210
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To inexpensively implement accurate AD conversion without using an expensive high-frequency PLL circuit in a power converter or relay requiring AD conversion of voltage, current, etc.SOLUTION: Synchronization of a PWM carrier with decimeter operation timing is implemented by using reference clock oscillators having frequencies slightly differing from each other. A synchronization correction function is implemented by minutely changing a frequency division ratio selection signal Msel by adjusting a decimation ratio M inside a modulation filter. As a synchronization reference signal, there are two types of signals of a synchronization timing signal Ts(m) and a carrier peak timing Tc(m).SELECTED DRAWING: Figure 1
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Inventors:
YAMAMOTO YASUHIRO
TAKIGUCHI MASASHI
TAKIGUCHI MASASHI
Application Number:
JP2016116953A
Publication Date:
December 21, 2017
Filing Date:
June 13, 2016
Export Citation:
Assignee:
MEIDENSHA ELECTRIC MFG CO LTD
International Classes:
H02M7/48; H03K7/08; H03M3/02
Attorney, Agent or Firm:
Hiromichi Kobayashi
Uzawa Hidehisa
Uzawa Hidehisa