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Title:
A designing support device, a design supporting method, and a program
Document Type and Number:
Japanese Patent JP5935563
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To design a semiconductor integrated circuit having good testability.SOLUTION: A design support device includes: a library 22; a creation unit 23; a division unit 24; and a deletion unit 25. The library 22 has information of a delay value that indicates time required from input to output of a signal for each of a plurality of computing units. The creation unit 23 creates a data flow diagram indicating the arrangement of the computing units and flip-flops on the basis of a source code 21 of a computer programming language and the library 22. The division unit 24 divides logic of the computing units in the data flow diagram so that the delay value satisfies constraints on a frequency and the number of input terminals to one output terminal of the computing units is equal to or less than a threshold value. The deletion unit 25 deletes the flip-flops between the computing units in the data flow diagram so that the sum of the delay values of the consecutive plurality of computing units satisfies the constraints on the frequency and the number of input terminals to one output terminal of the computing units is equal to or less than the threshold value.

Inventors:
Bamboo Saki Order
Chiwata Yukio
Shuji Hamada
Application Number:
JP2012159114A
Publication Date:
June 15, 2016
Filing Date:
July 17, 2012
Export Citation:
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Assignee:
Socionext Inc.
International Classes:
G06F17/50
Domestic Patent References:
JP10326297A
JP11295390A
Attorney, Agent or Firm:
Akinori Sakai