Title:
A detailed structure and multilevel interconnection board, a semiconductor package, and a manufacturing method of a detailed structure
Document Type and Number:
Japanese Patent JP6084709
Kind Code:
B2
Abstract:
The present invention is to provide a microstructure capable of improving the withstand voltage of an insulating substrate while securing fine conductive paths, a multilayer wiring board, a semiconductor package, and a microstructure manufacturing method. The microstructure of the present invention has an insulating substrate having a plurality of through holes, and conductive paths consisting of a conductive material containing metal filling the plurality of through holes, in which an average opening diameter of the plurality of through holes is 5 nm to 500 nm, an average value of the shortest distances connecting the through holes adjacent to each other is 10 nm to 300 nm, and a moisture content is 0.005% or less with respect to the total mass of the microstructure.
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Inventors:
Hirosuke Yamashita
Application Number:
JP2015558838A
Publication Date:
February 22, 2017
Filing Date:
January 19, 2015
Export Citation:
Assignee:
FUJIFILM Corporation
International Classes:
H01R11/01; C25D1/00; C25D7/00; C25D11/04; C25D11/18; C25D11/20; C25D11/24; H01L23/12
Domestic Patent References:
| JP2013069629A | 2013-04-18 | |||
| JP2012084294A | 2012-04-26 | |||
| JPH02119010A | 1990-05-07 | |||
| JP2011181350A | 2011-09-15 |
Other References:
JPN7016003428; 神戸大学大学院、地球惑星科学専攻: '電気伝導度（比抵抗）' 大陸・海底ダイナミック研究室 ＨＰ , 20130718, 神戸大学大学院、地球惑星科学専攻
Attorney, Agent or Firm:
Nozomi Watanabe
Haruko Sanwa
Hideaki Ito
Fumio Mitsuhashi
Haruko Sanwa
Hideaki Ito
Fumio Mitsuhashi