Devices and methods that involve accessing distributed subblocks of memory cells

Title:

Devices and methods that involve accessing distributed subblocks of memory cells

Document Type and Number:

Japanese Patent JP6321650

Kind Code:

B2

Abstract:

Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

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Inventors:

Toru Tanzawa

Application Number:

JP2015528581A

Publication Date:

May 09, 2018

Filing Date:

August 20, 2013

Export Citation:

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Assignee:

APPLIED MATERIALS,INCORPORATED

International Classes:

G11C16/08; G11C16/22

Domestic Patent References:

JP2007520842A
JP2000195252A
JP200795222A

Foreign References:

US7505328

Attorney, Agent or Firm:

Yoshiyuki Osuga
Nomura Yasuhisa

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