Title:
負荷の下で基板を検査する装置及び方法
Document Type and Number:
Japanese Patent JP4990486
Kind Code:
B2
Abstract:
The arrangement has a temperature control station (2) that is connected to a prober (1) through a handling system (3) only during testing. The temperature control station applies thermal, mechanical, electrical, physical or other chemical load to the semiconductor wafer and then transfers the wafer to prober through handling system for further testing. An independent claim is also included for method of testing semiconductor wafer under load.
Inventors:
Stephan schneidevent
Klaus Dietrich
Frank-Michael Werner
Don Feuerstein
Mike Lancaster
Dennis Place
Klaus Dietrich
Frank-Michael Werner
Don Feuerstein
Mike Lancaster
Dennis Place
Application Number:
JP2004249235A
Publication Date:
August 01, 2012
Filing Date:
August 27, 2004
Export Citation:
Assignee:
Cascade Microtech Dresden Gesellschaft Mito Beschlenktel Haftung
International Classes:
G01R1/06; G01R31/28; H01L21/66; H01L21/00
Domestic Patent References:
| JP7130817A | ||||
| JP10163280A | ||||
| JP2003179109A | ||||
| JP11074321A | ||||
| JP61168236A | ||||
| JP6342837A | ||||
| JP5343497A |
Foreign References:
| WO2001080289A1 |
Attorney, Agent or Firm:
Mitsufumi Esaki
Blacksmith
Ryota Imamura
Kiyota Eisho
Blacksmith
Ryota Imamura
Kiyota Eisho