Title:
モジュラー乗算を行うための装置、および、モジュラー乗算を行うための算術演算装置
Document Type and Number:
Japanese Patent JP3939658
Kind Code:
B2
Abstract:
A multiplicand is multiplied by a multiplier using a modulus. The multiplicand, the multiplier and the modulus are polynomials of variable. A multiplication look-ahead method to obtain a multiplication shift value is carried out. An intermediate result polynomial is shifted to the left by the number of digits of the multiplication shift value. A reduction shift value equalling the difference of the degree of the shifted intermediate result polynomial and the degree of the modulus polynomial is obtained in a reduction look-ahead method. The modulus polynomial is then shifted by a number of digits equalling the reduction shift value. In a three-operands addition, the shifted polynomial and the multiplicand are summed and the shifted modulus polynomial is subtracted. The modular multiplication are iteratively executed and processed progressively until all the powers of the multiplier polynomial have been processed. With a carry disabling function Z/NZ arithmetic and GF arithmetic can be carried out on a single long number calculating unit.
Inventors:
Elbe, Aslit
Zedrac, Holger
Jansen, Norbert
Seiffert, Jean-Pierre
Zedrac, Holger
Jansen, Norbert
Seiffert, Jean-Pierre
Application Number:
JP2002566769A
Publication Date:
July 04, 2007
Filing Date:
January 24, 2002
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
G06F7/72
Domestic Patent References:
| JP11212951A | ||||
| JP63018387A |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office
Kenzo Hara
Ryuichi Kijima
Ichiro Kaneko
Kenzo Hara
Ryuichi Kijima
Ichiro Kaneko