Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
デジタル論理回路、シフトレジスタ、およびアクティブマトリクス装置
Document Type and Number:
Japanese Patent JP5307157
Kind Code:
B2
Abstract:
A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and drain connected to a third circuit node and the second circuit node, respectively. A fifth transistor has a gate and drain connected to the first and third nodes, respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement.

Inventors:
Patrick Zebedee
Jaganus Rajendra
Application Number:
JP2010543935A
Publication Date:
October 02, 2013
Filing Date:
March 27, 2009
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
Sharp Corporation
International Classes:
H03K3/356; G02F1/133; G09G3/20; G09G3/36; G11C19/00; G11C19/28; H03K3/037; H03K19/0175; H03K19/094; H03K19/177; H03K23/40
Domestic Patent References:
JP58186217A
JP1160209A
JP2290320A
JP4352511A
JP5504871A
Attorney, Agent or Firm:
Kenzo Hara International Patent Office