Title:
The display panel containing the poor detecting method of wiring and a reverse multiplexing part, a poor detecting device, and a poor detecting device
Document Type and Number:
Japanese Patent JP6034033
Kind Code:
B2
Abstract:
Embodiments relate to a defect detecting method of a line (L1) and a demultiplexer (200), a defect detecting device (100), and a display panel including the defect detecting device (100). A demultiplexer (200) may connect a plurality of data lines (D1, D2, ..., Dm) to a plurality of corresponding lines (L1, L2,..., Lk). The defect detecting device includes DC lines (DC_R, DC_G, DC_B) supplied with respective DC voltages, first switches (T11, T12, ..., T1a) connected to the DC lines (DC_R, DC_G, DC_B) and configured to transmit the respective DC voltages to the corresponding first data lines (D1, D2, D3, D7, D8, D9) among a plurality of data lines (D1, D2, ..., Dm) according to a first gate signal, and second switches (T21, T22,..., T2b) connected to the first to third DC lines (DC_R, DC_G, DC_B) and configured to transmit one of the respective DC voltages to corresponding second data lines (D4, D5, D6, Dm-5, Dm-4, Dm-3) among a plurality of data lines (D1, D2, ..., Dm) according to a second gate signal.
Inventors:
Kaba Satoshi
Zheng Yin Tai
Zheng Yin Tai
Application Number:
JP2012067450A
Publication Date:
November 30, 2016
Filing Date:
March 23, 2012
Export Citation:
Assignee:
Samsung Display Co.,Ltd.
International Classes:
G09F9/00; G09F9/30; G09G3/20; G09G3/30; H01L51/50; H05B33/12
Domestic Patent References:
| JP2011186301A | ||||
| JP2004361427A |
Foreign References:
| WO2011089762A1 | ||||
| WO2010001590A1 |
Attorney, Agent or Firm:
Nobuyuki Matsunaga
Tetsuji Tsuji
Hidekazu Miyoshi
Masakazu Ito
Tetsuji Tsuji
Hidekazu Miyoshi
Masakazu Ito
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