Title:
プリスケーラ、分周器及びPLL回路
Document Type and Number:
Japanese Patent JP4015232
Kind Code:
B2
Abstract:
A prescaler which can be used in a PLL includes a counter section and an extender section. The counter section has a pair of staged, synchronous flip-flops which generate a frequency divided signal by frequency dividing an input oscillation signal by either two or three. The extender section has a plurality of staged, asynchronous flip-flops which generates a second frequency divided signal. A switching circuit connected between the extender section and the counter section controls whether the counter section operates as either a binary counter or a ternary counter. Power conservation is achieved by limiting the counter section to only a pair of flip-flops.
Inventors:
Morihito Hasegawa
Application Number:
JP20022397A
Publication Date:
November 28, 2007
Filing Date:
July 25, 1997
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K23/58; H03L7/197; H03K3/2885; H03K23/66; H03L7/193
Domestic Patent References:
| JP1091528A | ||||
| JP5090953A | ||||
| JP7221633A | ||||
| JP4302528A | ||||
| JP6258465A | ||||
| JP5048435A | ||||
| JP5347554A | ||||
| JP3136520A | ||||
| JP4274616A | ||||
| JP7170173A | ||||
| JP61062232A | ||||
| JP61280121A | ||||
| JP59094444U | ||||
| JP61023416A | ||||
| JP62122323A |
Other References:
角田秀夫著,「PLLの基本と応用」,日本,東京電機大学出版局,1979年 9月20日,120頁~124頁,パルス・スワロー・カウンタ、PLL
山本外史著,「精解演習 ディジタル回路」,日本,株式会社廣川書店,1974年 9月25日,198頁~231頁,帰還直列型のN進カウンタ
山本外史著,「精解演習 ディジタル回路」,日本,株式会社廣川書店,1974年 9月25日,198頁~231頁,帰還直列型のN進カウンタ
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda
Makoto Onda