Title:
駆動回路
Document Type and Number:
Japanese Patent JP7275984
Kind Code:
B2
Abstract:
A drive circuit includes a GaN FET having a source connected to an anode of an LD and a drain connected to a power source of the LD, a gate drive having an output port connected to a gate of the GaN FET and a negative voltage port connected to the source of the GaN FET to receive an input voltage at a positive voltage port and output the input voltage from the output port in response to a signal with a predetermined level, a capacitor between the positive and negative voltage ports of the gate drive, a diode on a power source line connecting the positive voltage port of the gate drive and a VDD power source for outputting a voltage less than the breakdown voltage at a voltage Vgs of the GaN FET, and a semiconductor switch between the source of the GaN FET and the ground.
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Inventors:
Masataka Yawada
Chihiro Miyahara
Chihiro Miyahara
Application Number:
JP2019147172A
Publication Date:
May 18, 2023
Filing Date:
August 09, 2019
Export Citation:
Assignee:
Omron Corporation
International Classes:
H01S5/042; H01S5/062
Domestic Patent References:
| JP2011238821A | ||||
| JP2011023474A | ||||
| JP2006310684A | ||||
| JP8096394A | ||||
| JP2017216812A |
Foreign References:
| US20180278017 |
Attorney, Agent or Firm:
Patent Attorney Corporation Shuwa Patent Office
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