Title:
A duty cycle equalization circuit and a method
Document Type and Number:
Japanese Patent JP6161633
Kind Code:
B2
Abstract:
A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.
Inventors:
Hertel, Yoga
Menorphy, Christian, First.
Toyful, Thomas, H.
Menorphy, Christian, First.
Toyful, Thomas, H.
Application Number:
JP2014555346A
Publication Date:
July 12, 2017
Filing Date:
January 15, 2013
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
H03K5/04
Domestic Patent References:
| JP2012178670A | ||||
| JP4266211A | ||||
| JP4326622A | ||||
| JP7106927A |
Foreign References:
| US20080150600 |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Fumio Koike
Tasaichi Tanae
Fumio Koike