Title:
POWER SUPPLY SUPPRESSION CIRCUIT AND POWER SUPPLY
Document Type and Number:
Japanese Patent JP2017103984
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a power supply suppression circuit which can suppress power supply to a power circuit and after, in the event of a failure of the power circuit.SOLUTION: A power supply suppression circuit includes: a latch circuit which, before the input of a fault signal indicative of a power circuit fault, outputs a power supply suppression signal indicating not to suppress power supply to the power circuit, whereas after the input of the fault signal, outputs a power supply suppression signal indicating to suppress power supply to the power circuit; a gate circuit which, when the power supply suppression signal indicating not to suppress power supply is input, outputs intact an input power on signal indicating the presence/absence of power supply to the power circuit, whereas when the power supply suppression signal indicating to suppress power supply is input, outputs a power supply instruction signal indicating to suppress power supply to the power circuit; and a power switch circuit which, when the power supply suppression signal indicating to suppress power supply is not input, supplies received power for the latch circuit to the latch circuit, whereas when the power supply suppression signal indicating to suppress power supply is input, feeds the power for the latch circuit from a built-in battery to the latch circuit.SELECTED DRAWING: Figure 1
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Inventors:
SUGIMOTO MOTOHIRO
Application Number:
JP2015237768A
Publication Date:
June 08, 2017
Filing Date:
December 04, 2015
Export Citation:
Assignee:
NEC PLATFORMS LTD
International Classes:
H02M3/00; H02H7/20
Domestic Patent References:
| JP2008035678A | 2008-02-14 | |||
| JP2012039199A | 2012-02-23 | |||
| JP2010257318A | 2010-11-11 | |||
| JPH08130839A | 1996-05-21 | |||
| JP2003219550A | 2003-07-31 |
Attorney, Agent or Firm:
Masahiko Desk
Naoki Shimosaka
Naoki Shimosaka