Title:
電子回路、位相ロックループ、送受信機回路、無線局、及び周波数分割の方法
Document Type and Number:
Japanese Patent JP6484354
Kind Code:
B2
Abstract:
Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.
More Like This:
| JPH0832445 | FREQUENCY DIVIDER CIRCUIT |
| JPS57207947 | SUBTRACTION COUNTER CIRCUIT |
| JPS5992493 | SEMICONDUCTOR INTEGRATED CIRCUIT |
Inventors:
Ek, Stafan
Paulson, Tony
Fernand, Henrik
Paulson, Tony
Fernand, Henrik
Application Number:
JP2017565047A
Publication Date:
March 13, 2019
Filing Date:
June 16, 2015
Export Citation:
Assignee:
Telefon Acty Bora Get Erm Ericson (Pubble)
International Classes:
H03K21/00; H03L7/08; H03L7/193
Domestic Patent References:
| JP2006526946A | ||||
| JP2010041466A | ||||
| JP2012085265A | ||||
| JP2008172512A | ||||
| JP2007053770A |
Foreign References:
| WO2010004747A1 | ||||
| US20070139088 | ||||
| US20040036513 | ||||
| US6542013 |
Attorney, Agent or Firm:
Yasunori Otsuka
Yasuhiro Otsuka
Shiro Takayanagi
Osamu Shimoyama
Takashi Sakamoto
Takahiro Oto
Yoshito Haruto
Koji Maeda
Mioko Watanabe
Yasuhiro Otsuka
Shiro Takayanagi
Osamu Shimoyama
Takashi Sakamoto
Takahiro Oto
Yoshito Haruto
Koji Maeda
Mioko Watanabe