Title:
バイナリ信号を増幅するための増幅器を有する電子回路
Document Type and Number:
Japanese Patent JP4304063
Kind Code:
B2
Abstract:
An electronic circuit comprising an amplifier (AMP) for amplifying a binary input signal (Ui) including an input stage coupled to receive the binary input signal (Ui) comprising means for supplying a DC current to the input stage. The means supplies a current having a first (I1) current value to the input stage during a period of time that is approximately equal to the period of time corresponding to a transition phase from a first binary signal value to a second binary signal value. During the remaining time, the means supplies a current having a second (I2) current value which is smaller than the first (I1) current value. By virtue thereof, the electronic circuit only consumes a significant amount of power during a transition phase from the first binary signal value to the second binary signal value. The amplifier (AMP) can be implemented in all kinds of digital circuits, of which the digital voltage range (the difference between the second and the first binary values) must be increased. For example, in oscillators that supply many clock phases, a substantial saving in power can be obtained by applying said amplifier (AMP) instead of prior-art amplifiers.
Inventors:
Denvesten Gerrit W
Application Number:
JP2003516150A
Publication Date:
July 29, 2009
Filing Date:
July 25, 2002
Export Citation:
Assignee:
NXP B.V.
International Classes:
H03K3/0231; H03K3/354; H03F3/34; H03F3/45; H03K3/012; H03K3/356; H03K5/02; H03K5/24
Domestic Patent References:
| JP60217723A | ||||
| JP973791A | ||||
| JP2003506815A | ||||
| JP2001177380A | ||||
| JP1013210A | ||||
| JP8116242A |
Foreign References:
| US6239624 | ||||
| US5306970 |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Takeshi Sekine
Takahashi
Hidetoshi Tachibana
Takeshi Sekine
Takahashi