Title:
分周器およびこの分周器を組み込む電子装置
Document Type and Number:
Japanese Patent JP2007508767
Kind Code:
A
Abstract:
The frequency divider for high-frequency clock signal comprises: a shift register ( 8 ) having cells ( 10 - 13 ) for storing each bit of an initial word, said cells being series connected in a loop ( 14 ), and said shift register being capable of shifting each bit of the initial word from the cell in which it is stored to the next cell in the loop at a rate clocked by the high-frequency clock signal, and wherein an output terminal ( 6 ) for outputting a frequency-divided clock signal is connected to the output of one cell of the loop of series-connected cells.
Inventors:
Schulben, Duville
Patrick, Da, Silva
Patrick, Da, Silva
Application Number:
JP2006534846A
Publication Date:
April 05, 2007
Filing Date:
September 24, 2004
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
H03K23/54; H03K23/00
Domestic Patent References:
| JPH03262210A | 1991-11-21 | |||
| JPH0575444A | 1993-03-26 | |||
| JPH1168555A | 1999-03-09 |
Foreign References:
| EP1244214A1 | 2002-09-25 | |||
| US6009139A | 1999-12-28 | |||
| WO2003073244A2 | 2003-09-04 |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki