Title:
カオス演算モジュールのための装置、及び方法
Document Type and Number:
Japanese Patent JP4395517
Kind Code:
B2
Abstract:
A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.
Inventors:
Ditt, William Elle.
Murali, Krishnamurti
Sinha, Sudeshna
Murali, Krishnamurti
Sinha, Sudeshna
Application Number:
JP2006534337A
Publication Date:
January 13, 2010
Filing Date:
October 07, 2004
Export Citation:
Assignee:
University of Florida Research Foundation, Inc.
International Classes:
G06F7/00; G06F7/38; G06F17/50; G06G7/00; G06G7/38; G06N7/08; H03K17/693; H03K19/173; H03K19/20; G06F
Domestic Patent References:
| JP5136688A | ||||
| JP9121026A |
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda
Makoto Onda