Title:
デューティサイクルの修正および任意の位相シフトを伴った、プログラム可能な偶数クロック分割器回路
Document Type and Number:
Japanese Patent JP3830940
Kind Code:
B2
Abstract:
A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.
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Inventors:
Nguyen, Andy Tea
Application Number:
JP2003526001A
Publication Date:
October 11, 2006
Filing Date:
August 16, 2002
Export Citation:
Assignee:
XILINX INCORPORATED
International Classes:
H03K23/00; G06F1/08; G06F7/68
Domestic Patent References:
| JP8179847A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai