Title:
高速周波数分周器及びそれを用いる位相同期ループ
Document Type and Number:
Japanese Patent JP5893026
Kind Code:
B2
Abstract:
A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.
Inventors:
Curtic Sabrai
Danya Kay
Danya Kay
Application Number:
JP2013524169A
Publication Date:
March 23, 2016
Filing Date:
August 09, 2011
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
Texas Instruments Incorporated
Texas Instruments Incorporated
International Classes:
H03K27/00; H03K23/64; H03L7/08; H03L7/183
Domestic Patent References:
| JP3136520A | ||||
| JP4117816A | ||||
| JP2005508577A |
Foreign References:
| WO2010022366A1 | ||||
| US20050058236 |
Attorney, Agent or Firm:
Kyozo Katayose