Title:
Integrated chip and method for forming integrated chip
Document Type and Number:
Japanese Patent JP6323961
Kind Code:
B2
Abstract:
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.
Inventors:
Mizumune Ren
Vermilion
Hirotatsu Hayashi
Kure Taisei
Zhang Yaning
King haruka
Vermilion
Hirotatsu Hayashi
Kure Taisei
Zhang Yaning
King haruka
Application Number:
JP2016202765A
Publication Date:
May 16, 2018
Filing Date:
October 14, 2016
Export Citation:
Assignee:
Taiwan Semiconductor Manufacturing Company,Ltd.
International Classes:
H01L27/11565; H01L21/336; H01L27/10; H01L27/11531; H01L27/11573; H01L29/788; H01L29/792
Domestic Patent References:
| JP2008004724A | ||||
| JP2015008226A | ||||
| JP2004273962A | ||||
| JP59011619A |
Attorney, Agent or Firm:
Eternal patent business corporation