【発明の名称】分周回路及びパルス信号作成回路

Title:

【発明の名称】分周回路及びパルス信号作成回路

Document Type and Number:

Japanese Patent JP2853894

Kind Code:

B2

Abstract:

A frequency divider includes three or more master-slave type flip-flop's (10,20,30) which are connected to each other to construct a 1/N frequency divider, in which two or more outputs whose periods are the same but phases are different are taken out from a master stage and a slave stage of each flip-flop, respectively and then those signals are composed to obtain a 1/(N/2) dividing output signal. As a result, a dividing output signal whose period does not vary with time can be obtained and also when the N is an even number, the output signal whose duty ratio is 1/2 can be further obtained. A pulse signal former (42,51,52) includes a differential amplifier to which two signals whose periods and pulse widths are the same but phases are different from each other by a pulse signal, and an output obtained by comparing those two signals is output from the pulse signal former. As a result, an output signal whose duty ratio is 1/2 is obtained.

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JPS60233934

COUNTER CIRCUIT

Inventors:

MAEMURA KIMIMASA

Application Number:

JP22340690A

Publication Date:

February 03, 1999

Filing Date:

August 24, 1990

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