Title:
遊技機
Document Type and Number:
Japanese Patent JP7464343
Kind Code:
B2
Abstract:
To prevent interrupt processing from being executed in an overlapping manner after the interrupt processing is completed.SOLUTION: A value of an 8-bit counter can be updated. When the 8-bit counter times out, predetermined information indicating that an interrupt request has been made is stored in an interrupt waiting monitor register. Interrupt processing (I_INTR) is executed on the basis of the specified information stored in the interrupt waiting monitor register. Interrupt is prohibited while the interrupt processing is being executed (step S2890 (IFF1=0, IFF2=0)). When the interrupt processing is completed, a return instruction (step S2893) is executed after an interrupt permission instruction is executed (step S2892). When the predetermined information is stored in the interrupt waiting monitor register during the interrupt processing, the interrupt processing is executed after the return instruction is executed.SELECTED DRAWING: Figure 232
Inventors:
Koichi Okamoto
Ryosuke Kaneda
Noriyuki Shikata
Masaki Hosokawa
Yuiso Taniguchi
Ryosuke Kaneda
Noriyuki Shikata
Masaki Hosokawa
Yuiso Taniguchi
Application Number:
JP2020175948A
Publication Date:
April 09, 2024
Filing Date:
October 20, 2020
Export Citation:
Assignee:
Sammy Corporation
International Classes:
A63F5/04
Domestic Patent References:
| JP7277787B2 | ||||
| JP7277792B2 | ||||
| JP7364908B2 | ||||
| JP2004248986A | ||||
| JP2011092515A | ||||
| JP2006150145A | ||||
| JP2005027938A | ||||
| JP2011224169A | ||||
| JP2016123515A |
Attorney, Agent or Firm:
Tadashi Nakamura