PURPOSE: To surely transfer an abnormality signal by forming a second logic circuit for inputting an output of a first logic circuit and inverting and outputting it, and sending out an output of a first logic circuit and an output of a second logic circuit to a logic circuit of the next stage.
CONSTITUTION: In a first logic circuit 3, signals of input terminals IN1-IN3 are inputted to a logical gate 1-1 and to a second logic circuit 4, a signal obtained by inverting an output of the circuit 3 by an inverter, and a signal of the terminal IN1 are inputted. In this case, the terminal IN1 becomes an H level and to the IN2 and the IN3, a signal of is inputted simultaneously, respectively. In that case, under the condition that an abnormality signal is outputted, when the gates 1-1, 1-2 are set as AND gates, an output of the gate 1-1 and an output of the gate 1-2 become '1' and '0', respectively at the time of the condition for outputting the abnormality signal. In this case, an output of the next logic circuit 5 becomes '1', and at the timing of an inspection timing signal TT, the abnormality signal is sent out of an output terminal Q of an FF 6.