Title:
An information processor and a memory test method
Document Type and Number:
Japanese Patent JP5915764
Kind Code:
B2
Abstract:
An information processing device includes a storage unit and a processor. The storage unit stores margin information, which stores a specified margin indicating a length of time in which signal processing is operated normally, in association with the type of a memory and the operation environment. The processor causes the memory to perform signal processing. The processor also changes an operation timing and specifies a range of operation timings with which the signal processing may be performed normally. Furthermore, the processor acquires the specified range of the operation timing as a measured margin, and extracts a specified margin associated with a combination of the type of memory and the operation environment of a current information processing device from the margin information. Then, the processor judges that the memory is not operating normally in the information processing device when the acquired measured margin is shorter than the extracted specified margin.
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Inventors:
Shinji Agata
Daisuke Harada
Daisuke Harada
Application Number:
JP2014544153A
Publication Date:
May 11, 2016
Filing Date:
October 31, 2012
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/00; G06F12/16
Domestic Patent References:
| JP2010157113A | 2010-07-15 | |||
| JP2010198328A | 2010-09-09 |
Foreign References:
| WO2012131796A1 | 2012-10-04 | |||
| US20080071966A1 | 2008-03-20 | |||
| US20070223288A1 | 2007-09-27 |
Attorney, Agent or Firm:
Yoshiyuki Osuga
virtue Tamio Ei
virtue Tamio Ei