Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
INPUT SIGNAL AMPLIFYING CIRCUIT
Document Type and Number:
Japanese Patent JPH0818367
Kind Code:
A
Abstract:

PURPOSE: To decrease input sensitivity characteristics of the input signal amplifying circuit formed of plural stages of inverters by connecting the input and output terminals of the inverter in the initial stage through a high resistance and connecting a resistance to a source voltage terminal.

CONSTITUTION: The input signal amplifying circuit is formed by connecting the inverters 1, and 5-7 in plural stages. The high resistance 4 is connected between the input terminal 2 and output terminal 3 of the inverter 1 of the initial stage and the resistance 10 is connected between the input terminal and a ground source voltage. An input voltage is biased by those resistance 4 and voltage dividing resistance 10 to lower than an output voltage, and a shift in operation point is caused to lower the input sensitivity characteristics. Consequently, an input signal amplifier of simple constitution which does not operate below a specific amplitude is obtained and an error signal, a noise, etc., are prevented from being misamplified.


Inventors:
TASAI FUMIHIRO
YAMASE SHINYA
MIYASHITA HIROYUKI
KIMURA KAZUHIRO
KANAYAMA HIROYOSHI
KANEKO HIROSHI
Application Number:
JP14986394A
Publication Date:
January 19, 1996
Filing Date:
June 30, 1994
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SANYO ELECTRIC CO
International Classes:
H03G11/00; H03K5/08; (IPC1-7): H03G11/00
Attorney, Agent or Firm:
Kei Okada