Title:
位相制御ループを具える集積回路
Document Type and Number:
Japanese Patent JP4256491
Kind Code:
B2
Abstract:
The phase control loop incorporates a divider (4) provided with an input connected to the oscillator (3) output and with an output for supplying a signal, the frequency of which is divided in relation to that of a signal applied at its input, and a phase comparator (1) provided with two inputs. One of the phase comparator inputs is intended to receive a reference signal (CKREF) and the other is connected to the divider (4) output. The phase comparator (1) is also provided with an output connected to the divider output and with an output connected to the oscillator regulating input. The resynchronisation module is a type D toggle.
Inventors:
エルヴェ マリ
Application Number:
JP8324598A
Publication Date:
April 22, 2009
Filing Date:
March 30, 1998
Export Citation:
Assignee:
エヌエックスピー ビー ヴィ
International Classes:
G06F1/08; H03L7/08; G06F1/12; G09G3/36; H03L7/081; H03L7/183
Attorney, Agent or Firm:
大倉 昭人
杉村 憲司
澤田 達也
杉村 憲司
澤田 達也