Title:
インバータ回路
Document Type and Number:
Japanese Patent JP7150123
Kind Code:
B2
Abstract:
The semiconductor device includes a first transistor, a second transistor, a first power supply wiring, and a second power supply wiring. The first transistor and the second transistor are stacked. The first power supply wiring and the second power supply wiring are stacked. The second power supply wiring and the first power supply wiring at least partly overlap with each other. The second power supply wiring and the first power supply wiring are substantially parallel to each other. A source electrode of the first transistor is electrically connected to the first power supply wiring. A source electrode of the second transistor is electrically connected to the second power supply wiring. The second transistor is an n-channel transistor, and a channel formation region is formed using an oxide semiconductor. The first transistor is a p-channel transistor, and a channel formation region is formed using silicon.
Inventors:
Kiyoshi Kato
Application Number:
JP2021177495A
Publication Date:
October 07, 2022
Filing Date:
October 29, 2021
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/8238; H01L21/82; H01L21/8239; H01L21/8242; H01L27/00; H01L27/088; H01L27/092; H01L27/105; H01L27/108; H01L27/1156; H01L29/786
Domestic Patent References:
| JP2013243352A | ||||
| JP2013243353A | ||||
| JP2003152191A |
Foreign References:
| WO2012176422A1 |